Integrated Fan-Out Package on Package Structure and Methods of Forming Same

ABSTRACT

An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.

BACKGROUND

The semiconductor industry has experienced rapid growth due tocontinuous improvements in the integration density of a variety ofelectronic components (e.g., transistors, diodes, resistors, capacitors,etc.). For the most part, this improvement in integration density hascome from repeated reductions in minimum feature size (e.g., shrinkingthe semiconductor process node towards the sub-20 nm node), which allowsmore components to be integrated into a given area. As the demand forminiaturization, higher speed and greater bandwidth, as well as lowerpower consumption and latency has grown recently, there has grown a needfor smaller and more creative packaging techniques of semiconductordies.

As semiconductor technologies further advance, stacked semiconductordevices, e.g., 3D integrated circuits (3DIC), have emerged as aneffective alternative to further reduce the physical size of asemiconductor device. In a stacked semiconductor device, active circuitssuch as logic, memory, processor circuits and the like are fabricated ondifferent semiconductor wafers. Two or more semiconductor wafers may beinstalled on top of one another to further reduce the form factor of thesemiconductor device.

Two semiconductor wafers or dies may be bonded together through suitablebonding techniques. The stacked semiconductor devices may provide ahigher density with smaller form factors and allow for increasedperformance and lower power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1 though 5A and 5B illustrate cross-sectional views of variousintermediary stages of forming a semiconductor device package inaccordance with some embodiments.

FIGS. 6 through 10 illustrate cross-sectional views of variousintermediary stages of forming a semiconductor device package inaccordance with some other embodiments.

FIGS. 11 through 13 illustrate cross-sectional views of variousintermediary stages of forming a semiconductor device package inaccordance with some other embodiments.

FIG. 14 illustrates a process flow for forming a semiconductor devicepackage in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Various embodiments include a package on package (PoP) structure havingat least two bonded device packages. A top one of device packagesincludes a first semiconductor die with a thermal interfacing material(TIM) on a back surface of the first semiconductor die. A bottom one ofthe device packages is bonded to the top device package, and the TIM mayalso form an interface with the bottom device package. For example, theTIM may contact a second semiconductor die in the bottom device package.Thus, heat from the bottom package may be advantageously dissipated tothe top package and, for example, to a heat spreader disposed on anopposing surface of the top package as the bottom package. Thus, thermalperformance and reliability in an embodiment package may be improved.The heat spreader may further improve the stiffness of the top package,which may advantageously reduce warpage.

FIGS. 1 through 5B illustrates various cross-sectional views of forminga device package 100 according to some embodiments. Referring first toFIG. 1, a cross-sectional view of a semiconductor die 102 is provided.Die 102 may include a semiconductor substrate, active devices, and aninterconnect structure (not individually illustrated). The substrate maycomprise, for example, bulk silicon, doped or undoped, or an activelayer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOIsubstrate comprises a layer of a semiconductor material, such assilicon, formed on an insulator layer. The insulator layer may be, forexample, a buried oxide (BOX) layer or a silicon oxide layer. Theinsulator layer is provided on a substrate, such as a silicon or glasssubstrate. Alternatively, the substrate may include another elementarysemiconductor, such as germanium; a compound semiconductor includingsilicon carbide, gallium arsenic, gallium phosphide, indium phosphide,indium arsenide, and/or indium antimonide; an alloy semiconductorincluding SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; orcombinations thereof. Other substrates, such as multi-layered orgradient substrates, may also be used.

Active devices such as transistors, capacitors, resistors, diodes,photo-diodes, fuses, and the like may be formed at the top surface ofthe substrate. An interconnect structure may be formed over the activedevices and the substrate. The interconnect structure may includeinter-layer dielectric (ILD) and/or inter-metal dielectric (IMD) layerscontaining conductive features (e.g., conductive lines and viascomprising copper, aluminum, tungsten, combinations thereof, and thelike) formed using any suitable method. The ILD and IMDs may includelow-k dielectric materials having k values, for example, lower thanabout 4.0 or even 2.0 disposed between such conductive features. In someembodiments, the ILD and IMDs may be made of, for example,phosphosilicate glass (PSG), borophosphosilicate glass (BPSG),fluorosilicate glass (FSG), SiO_(x)C_(y), Spin-On-Glass,Spin-On-Polymers, silicon carbon material, compounds thereof, compositesthereof, combinations thereof, or the like, formed by any suitablemethod, such as spinning, chemical vapor deposition (CVD), andplasma-enhanced CVD (PECVD). The interconnect structure electricallyconnect various active devices to form functional circuits within die102. The functions provided by such circuits may include memorystructures, processing structures, sensors, amplifiers, powerdistribution, input/output circuitry, or the like. One of ordinary skillin the art will appreciate that the above examples are provided forillustrative purposes only to further explain applications of variousembodiments and are not meant to limit these embodiments in any manner.Other circuitry may be used as appropriate for a given application.

Input/output (I/O) and passivation features may be formed over theinterconnect structure. For example, contact pads 104 may be formed overthe interconnect structure and may be electrically connected to theactive devices through the various conductive features in theinterconnect structure. Contact pads 104 may comprise a conductivematerial such as aluminum, copper, and the like. Furthermore, apassivation layer 106 may be formed over the interconnect structure andthe contact pads. In some embodiments, passivation layer 106 may beformed of non-organic materials such as silicon oxide, un-doped silicateglass, silicon oxynitride, and the like. Other suitable passivationmaterials may also be used. Portions of passivation layer 106 may coveredge portions of the contact pads 104.

Additional interconnect features, such as additional passivation layers,conductive pillars, and/or under bump metallurgy (UBM) layers, may alsobe optionally formed over contact pads 104. For example, as illustratedby FIG. 1, conductive pillars 108 may be formed on and electricallyconnect to contact pads 104, and a dielectric layer 109 may be formedaround such conductive pillars 108.

The various features of die 102 may be formed by any suitable method andare not described in further detail herein. Although referred to as adie herein, one or more features of die 102 may be formed while die 102is part of a larger substrate, for example, a wafer (not illustrated).After formation, die 102 may be singulated from other structures (e.g.,other dies) in the wafer. Furthermore, the general features andconfiguration of die 102 described above are but one example embodiment,and die 102 may include any combination of any number of the abovefeatures as well as other features.

As further illustrated by FIG. 1, die 102 is attached to a carrier 110by a die attach film (DAF) 112. Carrier 110 may be a glass or ceramiccarrier and may provide temporary mechanical and structural support todie 102 during subsequent processing steps. In this manner, damage tothe die 102 is reduced or prevented. In an embodiment, DAF 112 may beany suitable adhesive, such as an ultraviolet (UV) glue, which loses itsadhesive property when exposed to UV lights.

Furthermore, TIVs 114 may be formed over carrier 110 prior to theattachment of die 102. TIVs 114 may comprise copper, nickel, silver,gold, and the like for example, and may be formed by any suitableprocess. For example, a seed layer (not shown) may be formed overcarrier 110, and a patterned photoresist (not shown) having openings maybe used to define the shape of TIVs 114. The openings may expose theseed layer, and the openings may be filled with a conductive material(e.g., in an electro-chemical plating process, electroless platingprocess, and the like). Subsequently, the photoresist may be removed inan ashing and/or wet strip process, leaving TIVs 114 over carrier 110.TIVs 114 can also be formed using copper wire stud by copper wire bondprocesses (e.g., where mask, photoresist, and copper plating are notrequired). Excess portions of the seed lay may then be removed using acombination of photolithography and/or etching, for example.

Subsequently, in FIG. 2, a molding compound 116 is formed around die 102and TIVs 114. In embodiments molding compound 116 comprises an epoxy, aresin, a moldable polymer such as PBO, a molded underfill (MUF), oranother moldable material. In some embodiments, molding compound 116 maybe shaped or molded using for example, a mold (not shown), which mayhave a border or other feature for retaining molding compound 116 whenapplied. Such a mold may be used to pressure mold molding compound 116around die 102 and TIVs 114 to force molding compound 116 into openingsand recesses, eliminating air pockets or the like in molding compound116. Subsequently, a curing process is performed to solidify moldingcompound 116. Other suitable processes, such as transfer molding,compressive molding, liquid encapsulent molding, and the like, may beused to form molding compound 116.

After molding compound 116 is formed around die 102, molding compound116 is reduced or planarized by, for example, grinding, CMP, etching, oranother process. In some embodiments, molding compound 116 is reduced sothat I/O structures of die 102 (e.g., conductive pillars 108) areexposed. The planarization may further result in top surfaces of dies102 being substantially level with TIVs 114 and molding compound 116.

FIG. 3 illustrates the formation of RDLs 118 over molding compound 116,die 102, and TIVs 114. RDLs 118 may extend laterally past edges of die102 over a top surface of molding compound 116. RDLs 118 may includeconductive features 120 formed in one or more polymer layers 122.Polymer layers 122 may be formed of any suitable material (e.g.,polyimide (PI), polybenzoxazole (PBO), benzocyclobuten (BCB), epoxy,silicone, acrylates, nano-filled pheno resin, siloxane, a fluorinatedpolymer, polynorbornene, and the like) using any suitable method, suchas, a spin-on coating technique, lamination, and the like.

Conductive features 120 (e.g., conductive lines 120A and/or vias 120B)may be formed in polymer layers 122 and electrically connect to TIVs 114as well as conductive pillars 108 of die 102. The formation ofconductive features 120 may include patterning polymer layers 122 (e.g.,using a combination of photolithography and etching processes) andforming conductive features over and in the patterned polymer layer. Theformation of conductive features 120 may include depositing a seed layer(not shown), using a mask layer (not shown) having various openings todefine the shape of conductive features 120, and filling the openings inthe mask layer using an electro-chemical plating process, for example.The mask layer and excess portions of the seed layer may then beremoved. Thus, RDLs 118 are formed over die 102, TIVs 114, and moldingcompound 116. The number of polymer layers and conductive features ofRDLs 118 is not limited to the illustrated embodiment of FIG. 3. Forexample, RDLs 118 may include any number of stacked, electricallyconnected conductive features in multiple polymer layers.

As further illustrated by FIG. 3, carrier 110 and DAF 112 may be removed(e.g., after RDLs 118 are formed), and solder caps 124 may be formed onan opposing side of TIVs 114 as RDLs 118. Solder caps 124 may beelectrically connected to die 102 by TIVs 114 and RDLs 118. Thus, afirst device package 130 is formed. In subsequent process steps, soldercaps 124 may be used to bond device package 130 to other packagefeatures, such as another package in order to form an embodiment PoPstructure (e.g., see FIG. 5A).

FIG. 4 illustrates a cross-sectional view of a second device package150, which may be subsequently bonded to device package 130 inaccordance with some embodiments (e.g., see FIG. 5A). In an embodiment,device package 150 includes similar features as device package 130. Forexample, device package 150 may include a die 152 and a molding compound154 formed around and extending along sidewalls of die 152. Die 152 maycomprise similar features as die 102, and die 152 may or may not providea same functionality as die 102. For example, in an embodiment, die 102may be a memory die while die 152 may be a logic die providing controlcircuitry. Other embodiments may include dies providing differentfunctionality. Package 150 may further include TIVs 156 extendingthrough molding compound 154 and RDLs 158 formed over die 102, moldingcompound 154, and TIVs 156.

Device package 150 may further include additional features, such asexternal connectors 160 (e.g., BGA balls, C4 bumps, and the like) formedover RDLs 158. Connectors 160 may be disposed on UBMs 162, which mayalso be formed over RDLs 158. Connectors 160 may be electricallyconnected to die 152 and TIVs 156 by way of RDLs 158. Connectors 160 maybe used to electrically connect device package 150 (and subsequentlydevice package 100, see FIG. 5A) to other package components such asanother device die, interposers, package substrates, printed circuitboards, a mother board, and the like.

As further illustrated by FIG. 4, a TIM 164 may be formed (e.g.,dispensed) on an opposing side of device package 150 as RDLs 158. Forexample, TIM 164 may be formed on a surface of device package 150 to bebonded to device package 130 (see FIG. 5A). TIM 164 may comprise anysuitable material, such as a polymer having a good thermal conductivity,which may be between about 3 watts per meter kelvin (W/m·K) to about 5W/m·K or more. In an embodiment, TIM 164 may comprise an adhesive-typematerial, a gel-type material, or a combination thereof, such as amaterial provided by ShinETSU Silicones or Dow Corning. As explained ingreater detail below, TIM 164 may advantageously improve heatdissipation in the resulting bonded device package 100 by providing aheat dissipation path from device package 150 through device package130.

FIG. 5A illustrates a bonded device package 100 comprising devicepackage 130 bonded to device package 150. Packages 130 and 150 may bebonded, for example, by aligning and bonding solder caps 124 of package130 with TIVs 156 of package 150. Die 152 may be electrically connectedto die 102 by RDLs 158, TIVs 164, TIVs 114, and RDLs 118. Duringbonding, TIM 164 may be disposed between and contact both devicepackages 130 and 150. Device package 130 (e.g., die 102) may applypressure onto TIM 164 during, which may cause TIM 164 to spreadlaterally. In some embodiments, a reflow process is used to bond soldercaps 124 to TIVs 156, which may further cure TIM 164. Heat from devicepackage 150 may be dissipated through die 102 of device package 130 asillustrated by arrows 168.

TIM 164 may bridge a gap 170 between device packages 130 and 150, andTIM 164 may be formed to have a thickness T1 (e.g., measured between topand bottom surfaces of TIM 164) that is sufficiently large to bridge gap170. For example, in some embodiments, thickness T1 of TIM 164 may beabout 10 μm to about 50 μm. Furthermore, in a top down view (not shown),TIM 164 may cover a relatively large percentage of a bottom surface ofdie 102. For example, a surface area of TIM 164 may be at least about80% of a surface of area of a bottom surface of die 102. It has beenobserved that when TIM 164 has a surface area in this range, thermalperformance may be advantageously improved in the device package. Forexample, thermal performance in package 100 may include improvedefficiency and lowered thermal resistance by providing an additionalthermal dissipation path through die 102. In some embodiments, a surfacearea of TIM 164 may be larger than a surface area of die 102, and TIM164 may extend laterally past edges of die 102 to contact moldingcompound 116 (see e.g., FIG. 5B). In other embodiments, TIM 164 may onlypartially cover a bottom surface of die 102. For example, TIM 164 may belocalized and disposed only on hot spots (or other selective areas) ofdie 102 and/or bottom package 150 (e.g., hot spots on die 152) dependingon package design.

A heat spreader 172 may be attached to an opposing side of devicepackage 130 as device package 150 to further improve heat dissipation indevice package 100. For example, heat spreader 172 may disperse heattransmitted from dies 102 and 152. In some embodiments, heat spreader172 has a high thermal conductivity, for example, between about 200W/m·K to about 400 W/m·K or more, and may be formed using a metal, ametal alloy, or the like. For example, heat spreader 172 may comprisemetals and/or metal alloys such as Al, Cu, Ni, Co, combinations thereof,and the like. A second TIM 174 may attach heat spreader 170 to devicepackage 150. Heat spreader 172 may increase the rigidity of devicepackage 150, which advantageously reduces warpage in package 100. Thus,an embodiment PoP includes thermal management features thatadvantageously reduces warpage and improves thermal dissipation.Additional features may also be bonded to package 100. For example,another device die, interposers, package substrates, printed circuitboards, a mother board, and the like (not shown) may be bonded topackage 100 by connectors 160.

FIGS. 6 through 10 illustrate cross-sectional views of intermediarystages of manufacturing a device package 200 in accordance with somealternative embodiments. Package 200 may be similar to package 100 wherelike references numerals indicate like elements. Referring to FIG. 6, asemiconductor die 102 is attached to a carrier substrate 110 by a DAF112. A molding compound 116 is formed around and extending alongsidewalls of die 102. Top surfaces of molding compound 116 and die 102may be substantially level.

In FIG. 7, fan-out RDLs 118 are formed over die 102 and molding compound116. RDLs 118 maybe electrically connected to die 102, and RDLs mayextend laterally past die 102 onto molding compound 116. RDLs 118include various conductive features 120 formed in one or more polymerlayers 122. After RDLs 118 are formed, carrier 110 and DAF 112 may beremoved as illustrated by FIG. 8.

As further illustrated by FIG. 8, openings 202 may be patterned inmolding compound 116 using a laser ablation process, for example.Openings 202 may extend through molding compound 116 to exposeconductive features (not explicitly illustrated in FIG. 8) in RDLs 118.Next, in FIG. 9, solder balls 204 are formed in openings 202 using aball drop process, for example. Solder balls 204 may extend throughmolding compound 116, and a portion of solder balls 204 may furtherextend past a top surface of molding compound 116. Thus, a first package130 is formed according to some embodiments.

FIG. 10 illustrates package 130 bonded to a bottom package 150. Bottompackage 150 may include a die 152, a molding compound 154 around die152, RDLs 158 electrically connected to die 152, and external connectors(e.g., UBMs 162/connectors 160. Bottom package 150 may further includesolder balls 206 disposed in openings 208, which extend through moldingcompound 154. Solder balls 206 may be bonded to solder balls 204 inpackage 150. For example, solder balls 204 and 206 may be aligned,contacted, and reflowed in order to bond packages 130 and 150. Thusvarious features (e.g., dies 102 and 152 as well as RDLs 118 and 158) inpackages 130 and 150 may be electrically connected. In otherembodiments, bottom package 150 may include a different configuration.

A TIM 164 may be span a gap 170 between packages 130 and 150. Forexample, TIM 164 may contact a bottom surface of die 102 as well as atop surface of package 150 (e.g., die 152). Thus, TIM 164 may provide aheat dissipation path to from bottom package 150 through top package 130as indicated by arrows 168. A heat spreader 172 may further be attachedto a surface of package 130 opposing TIM 164. Thus, thermal performancemay be improved in package 200. Furthermore, heat spreader 172 mayadvantageously reduce warpage in package 200.

FIGS. 11 through 13 illustrate cross-sectional views of intermediarystages of manufacturing a package 300 in accordance with some otherembodiments. Package 300 may be similar to package 100 where likereferences numerals indicate like elements. Referring first to FIG. 11,a substrate 302 having conductive features 304 disposed therein. In anembodiment, conductive features 304 may be formed in one or moredielectric layers, which may include low-k dielectric materials. Inanother embodiments, substrate 302 is a package substrate, andconductive features 304 may be formed in one or more build-up layers. Insuch embodiments, substrate 302 may further include a package core andone or more through-vias electrically connecting conductive features onopposing sides of the package core.

A molding compound 306 (or other insulating material) may be formed overpackage substrate 302. Furthermore, molding compound 306 may include acavity 308 and one or more openings 310. Openings 310 and cavity 308 mayextend through molding compound 306 to expose conductive features (notshown) on package substrate 302. Openings 310 and cavity 308 may bepatterned in molding compound 306, for example, by laser drilling,photolithography, and/or other etching processes.

After openings 310 and cavity 308 are patterned, solder balls 312 may bedisposed in openings 310 as illustrated by FIG. 12. For example, a balldrop process may be used to disposed solder balls 312 in openings 310.As further illustrated by FIG. 12, die 102 may be at least partiallydisposed in cavity 308 and flip chip bonded to package substrate 302.For example, die 102 may include external connectors 312, which may besolder bumps, such as C4 bumps, microbumps, BGA balls, and the like. Invarious embodiments, cavity 308 may be patterned to have a sufficientlylarge surface area in order to accommodate die 302. For example, alateral dimension of cavity 308 may be larger than a lateral dimensionof die 302. Thus, a top package 320 may be formed. In other embodiments,top package 320 may include TIVs (e.g., similar to TIVs 114) with soldercaps (e.g., similar to solder caps 124) in lieu of or in addition tosolder balls 312 in openings 310.

FIG. 13 illustrates package 320 bonded to a bottom package 150. Bottompackage 150 may include a die 152, a molding compound 154 around die152, RDLs 158 electrically connected to die 152, and external connectors(e.g., UBMs 162/connectors 160. Bottom package 150 may further includesolder balls 314 in openings 316 extending through molding compound 154.Solder balls 314 may be bonded to solder balls 312 in package 320. Forexample, solder balls 314 and 312 may be aligned, contacted, andreflowed in order to bond packages 320 and 150. Thus various features(e.g., die 102, package substrate 302, die 152, and RDLs 118) inpackages 130 and 150 may be electrically connected. In otherembodiments, bottom package 150 may include a different configuration.

A TIM 164 may be bridge a gap 170 between packages 320 and 150. Forexample, TIM 164 may contact a bottom surface of die 102 as well as atop surface of package 150, Thus, TIM 164 may provide a heat dissipationpath to disperse heat from bottom package 150 through top package 320 asindicated by arrows 168. A heat spreader 172 may further be attached toa surface of package 320 opposing TIM 164. Thus, thermal performance maybe improved in package 300. Furthermore, heat spreader 172 mayadvantageously reduce warpage in package 300.

FIG. 14 illustrates a process flow 400 for forming a device package inaccordance with some embodiments. In step 402, a first package isprovided. The first package may include a semiconductor die (e.g., die102) having a back surface exposed. Throughout the description a backsurface may be used to describe a surface of a die or substrate opposinga side of the substrate having active devices and functional circuitsformed thereon. Next in step 404, a bottom package (e.g., package 150)is provided. A TIM (e.g., TIM 164) may be disposed on a top surface ofthe bottom package. In step 406, the top and bottom packages are bondedtogether so that the TIM contacts a bottom surface of the semiconductordie. The TIM may provide a thermal dissipation path from the bottompackage through the top package. Additional features may also beattached to the package. For example, a heat spreader (e.g., heatspreader 172) may be attached to an opposing side of the top package asthe bottom package.

Various embodiments include a device package having at least two bondeddevice packages with a TIM disposed between the two packages. The TIMmay contact a bottom surface of a semiconductor die in a top one of thedevice packages. Heat from the bottom package may be advantageouslydissipated to the top package and, for example, to a heat spreader overthe top package. Thus, thermal performance and reliability in anembodiment package may be improved. The heat spreader may furtherimprove the stiffness of the top package, which may advantageouslyreduce warpage.

In accordance with an embodiment, a package includes a first package; athermal interface material (TIM) contacting a top surface of the firstpackage, and a second package bonded to the first package. The secondpackage includes a first semiconductor die, and the TIM contacts abottom surface of the first semiconductor die. The package furtherincludes a heat spreader disposed on an opposing surface of the secondpackage as the first package.

In accordance with another embodiment, a package includes a first die, afirst molding compound extending along sidewalls of the first die, apolymer layer on a top surface of the first die, and a second die overand separated from the first die by a gap. The polymer layer spans thegap and contacts a bottom surface of the second die. The package furtherincludes a second molding compound extending along sidewalls of thesecond die and a heat spreader over the second die. The first moldingcompound and the second molding compound are separated by the gap.

In accordance with yet another embodiment, a method includes providing afirst package having a first semiconductor die, providing a secondpackage having a thermal interface material (TIM) on a top surface, andbonding the first package to the second package to form a bondedpackage. The TIM contacts a bottom surface of the first semiconductordie in the bonded package. The method further includes attaching a heatspreader to an opposing side of the first package as the TIM.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A package comprising: a first package comprising a firstsemiconductor die, wherein the first semiconductor die comprises a firstsemiconductor substrate; a thermal interface material (TIM) contacting atop surface of the first package; a second package bonded to the firstpackage, wherein the second package comprises a second semiconductordie, wherein the second semiconductor die comprises a secondsemiconductor substrate, and wherein the TIM contacts the firstsemiconductor substrate and the second semiconductor substrate; and aheat spreader disposed on an opposing surface of the second package asthe first package.
 2. The package of claim 1, wherein in a first surfacearea of the TIM is at least about eighty percent of a second surfacearea of the second semiconductor die.
 3. The package of claim 1, whereinthe TIM extends laterally past edges of the second semiconductor die. 4.The package of claim 1, wherein the second package further comprises: amolding compound around the second semiconductor die; a plurality ofthrough-vias extending through the molding compound; and solder caps oneach of the plurality of through-vias.
 5. The package of claim 1,wherein the second package further comprises: a molding compound aroundthe second semiconductor die; a plurality of openings extending throughthe molding compound; and a solder ball at least partially disposed ineach of the plurality of openings.
 6. The package of claim 1 furthercomprising fan-out redistribution layers (RDLs) disposed on an opposingside of the first semiconductor die as the TIM, wherein the fan-out RDLsextend laterally past edges of the second semiconductor die.
 7. Thepackage of claim 1 further comprising a substrate on an opposing side ofthe second semiconductor die as the TIM, wherein the secondsemiconductor die is flip chip bonded to the substrate.
 8. (canceled) 9.A package comprising: a first die comprising a first input/outputfeature disposed on a first semiconductor substrate, wherein the firstdie comprises a top surface disposed on an opposing side of the firstsemiconductor substrate as the first input/output feature; a firstmolding compound extending along sidewalls of the first die; a polymerlayer contacting the top surface of the first die; a second die over andseparated from the first die by a gap, wherein the second die comprisesa second input/output feature disposed on a second semiconductorsubstrate, wherein the polymer layer spans the gap and contacts a bottomsurface of the second die, and wherein the bottom surface of the seconddie is disposed on an opposing side of the second semiconductorsubstrate as the second input/output feature; and a second moldingcompound extending along sidewalls of the second die, wherein the firstmolding compound and the second molding compound are separated by thegap.
 10. The package of claim 9, wherein the polymer layer contacts abottom surface of the second molding compound.
 11. The package of claim9 further comprising: a heat dissipation feature over the second die;through inter-vias (TIVs) extending through the second molding compound;solder caps on the TIVs, wherein the solder caps are disposed in thegap; and conductive elements extending through the first moldingcompound and bonded to the solder caps.
 12. The package of claim 9further comprising: openings extending through the second moldingcompound; and solder balls disposed in the openings and gap, wherein thesolder balls are bonded to conductive elements in the first moldingcompound.
 13. The package of claim 9 further comprising fan-outredistribution layers (RDLs) between the second die and a heat spreaderover the second die.
 14. The package of claim 9, wherein the second dieis flip chip bonded to a package substrate, wherein the packagesubstrate is disposed between the second die and a heat spreader overthe second die.
 15. The package of claim 14, wherein the second die isdisposed in a cavity in the second molding compound, wherein a lateraldimension of the second molding compound is greater than a lateraldimension of the second die.
 16. The package of claim 9, wherein thepolymer layer is a thermal interface material, and wherein a firstsurface area of the polymer layer is at least eighty percent of a secondsurface area of the bottom surface of the second die. 17.-20. (canceled)21. A package comprising: a first semiconductor substrate; a firstmolding compound encapsulating the first semiconductor substrate,wherein a surface of the first molding compound is substantially levelwith a surface of the first semiconductor substrate; a polymer layer atleast partially contacting the surface of the first semiconductorsubstrate; a second semiconductor substrate disposed on an opposing sideof the polymer layer as the first semiconductor substrate, wherein asurface of the second semiconductor substrate contacts the polymerlayer; and a second molding compound extending along a sidewall of thesecond semiconductor substrate, wherein a surface of the second moldingcompound is substantially level with the surface of the secondsemiconductor substrate, and wherein the surface of the first moldingcompound is spaced apart from the surface of the second molding compoundby an air gap.
 22. The package of claim 21, wherein the polymer layercontacts the surface of the second molding compound.
 23. The package ofclaim 21, wherein the second molding compound is spaced apart from thesidewall of the second semiconductor substrate by an additional air gap.24. The package of claim 21, further comprising: first conductivefeatures extending through the first molding compound and electricallyconnected to first redistribution layers; and second conductive featuresextending through the second molding compound and electrically connectedto second redistribution layers, wherein the first redistribution layersand the second redistribution layers are disposed on opposing sides ofthe first semiconductor substrate, and wherein the second conductivefeatures are electrically connected to the first conductive features.